Bus Arbitration; Operation; Bus Transfer Timing - Renesas H8SX/1520 Series Hardware Manual

6.7

Bus Arbitration

This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). The internal
bus arbiter handles the CPU and DMAC accesses.
The bus arbiters decide priority at the prescribed timing, and permit use of the bus by means of the
bus request acknowledge signal.
6.7.1

Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The priority of the internal bus arbitration:
(High) DMAC > CPU (Low)
If the DMAC accesses continue, the CPU can be given priority over the DMAC to execute the bus
cycles alternatively between them by setting the IBCCS bit in BCR2.
6.7.2

Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority over that of the bus
master that has taken control of the bus and is currently operating, the bus is not necessarily
transferred immediately. There are specific timings at which each bus master can release the bus.
(1)
CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC, the
bus arbiter transfers the bus to the bus master that issued the request.
The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is
transferred synchronously with the clock.
Note, however, that the bus cannot be transferred in the following cases.
• The word or longword access is performed in some divisions.
• Stack handling is performed in multiple bus cycles.
Downloaded from Elcodis.com electronic components distributor
Section 6 Bus Controller (BSC)
Rev. 3.00 Mar. 14, 2006 Page 131 of 804
REJ09B0104-0300