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6.6
Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (T
) between
I
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
In the case of normal extended mode if an external write occurs after an external read while the
ICIS bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle.
In the case of multiplex extended mode if an external cycle occurs after an external read while the
ICIS bit is set to 1 in BCR, an idle cycle is inserted at the start of the external cycle after the
external read.
Figure 6.27 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.27 (a),
with no idle cycle inserted, a conflict occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.27 (b), an idle cycle is inserted, thus preventing data conflict.
Bus cycle A
Bus cycle B
Bus cycle A
Bus cycle B
T
T
T
T
T
T
T
T
T
T
T
1
2
3
1
2
1
2
3
I
1
2
φ
φ
Address bus
Address bus
Data bus
Data bus
Data conflict
Long output floating time
(a) No idle cycle insertion
(b) Idle cycle insertion
Figure 6.27 Examples of Idle Cycle Operation
Table 6.8 shows the pin states in an idle cycle.
Rev. 1.00, 09/03, page 128 of 704
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