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6.8
Idle Cycle
6.8.1
Operation
When this LSI accesses external address space, it can insert an idle cycle (T
in the following three cases: (1) when read accesses in different areas occur consecutively, (2)
when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs
immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the
IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and
so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Address bus
(area A)
(area B)
Data bus
(a) No idle cycle insertion
(ICIS1 = 0)
Bus cycle A
Bus cycle B
y
T
T
T
T
T
1
2
3
1
2
Long output floating time
Figure 6.44 Example of Idle Cycle Operation
(Consecutive Reads in Different Areas)
Bus cycle A
T
1
Address bus
(area A)
(area B)
Data bus
Data collision
(b) Idle cycle insertion
Rev. 2.00, 05/03, page 179 of 820
) between bus cycles
i
Bus cycle B
T
T
T
T
T
2
3
i
1
2
Idle cycle
(ICIS1 = 1, initial value)
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