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6.9
Idle Cycle
6.9.1
Operation
When the H8/3067 Group chip accesses external space, it can insert a 1-state idle cycle (T
between bus cycles in the following cases: (1) when read accesses between different areas occur
consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) immediately
after a DRAM space access. By inserting an idle cycle it is possible, for example, to avoid data
collisions between ROM, which has a long output floating time, and high-speed memory, I/O
interfaces, and so on.
The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted in
the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.43 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
φ
Address bus
RD
Data bus
(a) Idle cycle not inserted
Figure 6.43 Example of Idle Cycle Operation (1) (ICIS1 = 1)
Bus cycle A Bus cycle B
T
T
T
T
T
1
2
3
1
2
Data
Long buffer-off
collision
time
Section 6 Bus Controller
Bus cycle A Bus cycle B
T
T
1
2
φ
Address bus
RD
Data bus
(b) Idle cycle inserted
Rev. 4.00 Jan 26, 2006 page 199 of 938
)
I
T
T
T
T
3
i
1
2
REJ09B0276-0400
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