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Section 6 Bus Controller (BSC)
6.10
Idle Cycle
In this LSI, idle cycles can be inserted between the consecutive external accesses. By inserting the
idle cycle, data conflicts between ROM read cycle whose output floating time is long and an
access cycle from/to high-speed memory or I/O interface can be prevented.
6.10.1
Operation
When this LSI consecutively accesses external address space, it can insert an idle cycle between
bus cycles in the following three cases. These conditions are determined by the sequence of read
and write and previously accessed area.
1. When read cycles of different areas in the external address space occur consecutively
2. When an external write cycle occurs immediately after an external read cycle
3. When an external read cycle occurs immediately after an external write cycle
Up to four idle cycles can be inserted under the conditions shown above. The number of idle
cycles to be inserted should be specified to prevent data conflicts between the output data from a
previously accessed device and data from a subsequently accessed device.
Under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of
idle cycles can be selected from setting A specified by the bits IDLCA1 and IDLCA0 in IDLCR or
setting B specified by the bits IDLCB1 and IDLCB0 in IDLCR: Setting A can be selected from
one to four cycles, and setting B can be selected from one or two to four cycles. Setting A or B can
be specified for each area by setting the bits IDLSEL7 to IDLSEL0 in IDLCR. Note that the bits
IDLSEL7 to IDLSEL0 correspond to the previously accessed area of the consecutive accesses.
The number of idle cycles to be inserted under condition 3, which is a condition to insert idle
cycles after write, can be determined by setting A as described above.
After the reset release, IDLCR is initialized to four idle cycle insertion under all conditions 1 to 3
shown above.
Rev.2.00 Jun. 28, 2007 Page 198 of 666
REJ09B0311-0200
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