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Section 3 MCU Operating Modes
3.3
System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3067 Group.
Bit
7
SSBY
Initial value
0
Read/Write
R/W
Software standby
Enables transition to software standby mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 20, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7
SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
Rev. 4.00 Jan 26, 2006 page 66 of 938
REJ09B0276-0400
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
3
2
1
UE
NMIEG
SSOE
1
0
0
R/W
R/W
R/W
RAM enable
Enables or
disables
on-chip RAM
Software standby output port enable
Selects the output state of the address bus
and bus control signals in software standby mode
NMI edge select
Selects the valid edge
of the NMI input
0
RAME
1
R/W
(Initial value)
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