System Control Register 2 (Syscr2) (F-Ztat Version Only) - Renesas H8S Series Hardware Manual

Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: This bit cannot be modified and is always read as 0.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt
controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
0
1
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Bit 2—Reserved: This bit cannot be modified and is always read as 0.
This bit is reserved in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. Only 0 should be written to
this bit.
Bit 1—Reserved: Only 0 should be written to this bit.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status
is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
3.2.3

System Control Register 2 (SYSCR2) (F-ZTAT Version Only)

Bit : 7
—
Initial value : 0
R/W : —
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
SYSCR2 can only be accessed in the F-ZTAT version. In other versions, this register cannot be written to and will return
an undefined value if read.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Rev.6.00 Oct.28.2004 page 58 of 1016
REJ09B0138-0600H
Bit 4 Interrupt Control
INTM0 Mode
0 0
1 —
0 2
1 —
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
Description
On-chip RAM is disabled
On-chip RAM is enabled
6 5
— —
0 0
— —
Description
Control of interrupts by I bit
Setting prohibited
Control of interrupts by I2 to I0 bits and IPR
Setting prohibited
4 3 2
— FLSHE —
0 0 0
— R/W —
(Initial value)
(Initial value)
(Initial value)
1 0
— —
0 0
— —