System Control Register(Syscr) - Renesas H8S Series Hardware Manual

3.2.2

System Control Register(SYSCR)

SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and
enables or disables on-chip RAM.
Bit Bit Name Intial Value
7 MACS 0
6 — 0
5 INTM1 0
4 INTM0 0
3 NMIEG 0
2, 1 — All 0
0 RAME 1
R/W Descriptions
— MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for the MAC instruction
1: Saturating calculation for the MAC instruction
— Reserved
This bit is always read as 0 and cannot be modified.
R/W These bits select the control mode of the interrupt
R/W controller. For details of the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Setting prohibited
10: Interrupt control mode 2
11: Setting prohibited
R/W NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
— Reserved
These bits are always read as 0 and cannot be
modified.
R/W RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Section 3 MCU Operating Modes
Rev. 6.00 Mar 15, 2006 page 53 of 570
REJ09B0211-0600