ST STM32L4+ Series Reference Manual page 1220

Advanced-control timers (TIM1/TIM8)
Read CCR1H
S
read_in_progress
Read CCR1L
R
Input
CC1S[1]
mode
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
Figure 314. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)
ETRF
OC1REF
CNT>CCR1
Output
mode
CNT=CCR1
controller
(1)
OCxREF
OC5REF
OC1CE OC1M[3:0]
TIM1_CCMR1
1. OCxREF, where x is the rank of the complementary channel
1220/2301
Figure 313. Capture/compare channel 1 main circuit
APB Bus
MCU-peripheral interface
8
Capture/compare preload register
capture_transfer
Capture /compare shadow register
Capture
Counter
To the master mode
controller
OC1REFC
Output Dead-time
generator
selector
DTG[7:0]
TIM1_BDTR
RM0432 Rev 6
8
write_in_progress
compare_transfer
Comparator
'0'
x0
01
OC1_DT
11
TIM1_CCER
OC1N_DT
11
10
'0'
0x
CC1NE CC1E
TIM1_CCER
TIM1_CCER
write CCR1H
S
write CCR1L
R
Output
CC1S[1]
mode
CC1S[0]
OC1PE
UEV
(from time
base unit)
CNT>CCR1
CNT=CCR1
0
Output
enable
1
circuit
CC1P
0
Output
enable
1
circuit
CC1E TIM1_CCER
CC1NE
CC1NP MOE OSSI OSSR
TIM1_BDTR
OIS1 OIS1N
TIM1_CR2
RM0432
OC1PE
TIMx_CCMR1
MS31089V4
OC1
OC1N
MS35909V2