Advertisement
26.3.1
Instruction Register (SDIR)
SDIR is a 32-bit register. JTAG instructions can be transferred to SDIR by serial input from the
ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is in the
Test-Logic-Reset state, but is not initialized by a reset or in standby mode.
Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the
last 4 bits of the serial data will be stored in SDIR.
Bit
Bit Name
31
TS3
30
TS2
29
TS1
28
TS0
27 to
14
13
12
11
10 to 1
0
Initial
Value
R/W
Description
1
R/W
Test Set Bits
1
R/W
0000: EXTEST mode
1
R/W
0001: Setting prohibited
0
R/W
0010: CLAMP mode
0011: HIGHZ mode
0100: SAMPLE/PRELOAD mode
0101: Setting prohibited
1101: Setting prohibited
1110: IDCODE mode (Initial value)
1111: BYPASS mode
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
1
R
Reserved
This bit is always read as 1 and cannot be modified.
0
R
Reserved
This bit is always read as 0 and cannot be modified.
1
R
Reserved
This bit is always read as 1 and cannot be modified.
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
1
R
Reserved
This bit is always read as 1 and cannot be modified.
Section 26 Boundary Scan (JTAG)
:
:
Rev. 1.00 Mar. 12, 2008 Page 1023 of 1178
REJ09B0403-0100
Advertisement
