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28.1.2
Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit
Bit Name
7, 6
5
NESEL
4
EXCLE
3
2
PNCCS
1
PNCAH
0
Initial
Value
R/W
Description
0
R/W
Reserved
The initial value should not be changed.
0
R/W
Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (φSUB) input
from the EXCL pin is sampled using the clock (φ)
generated by the system clock pulse generator.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock
0
R/W
Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
0
R/W
Reserved
The initial value should not be changed.
0
R/W
Address Multiplex Chip Select
Controls the output polarity of chip select signals (CS256,
IOS) in the address multiplex extended mode.
0: Outputs CS256, and IOS
1: Outputs CS256, and IOS
0
R/W
Address Multiplex Address Hold
Controls the output polarity of the address hold signal (AH)
in the address multiplex extended mode.
0: Outputs AH
1: Outputs AH
0
R/W
Reserved
The initial value should not be changed.
Section 28 Power-Down Modes
Rev. 1.00 Mar. 12, 2008 Page 1061 of 1178
REJ09B0403-0100
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