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Section 28 Power-Down Modes
28.5
Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed
with the SSBY bit in SBYCR set to 1 and the PSS bit in TCSR (WDT_1) cleared to 0.
In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all
stop. However, the contents of the CPU registers, on-chip RAM data, I/O ports, and the states of
on-chip peripheral modules other than the PWMX, A/D converter, and part of the SCI are retained
as long as the prescribed voltage is supplied.
Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15), the USB
suspend/resume interrupt (RESUME), the RES pin input, or STBY pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When exiting software standby mode by IRQ0 to IRQ15
interrupt, set the corresponding enable bit to 1 and ensure that any interrupt with a higher priority
than IRQ0 to IRQ15 is not generated. Software standby mode is not exited if the corresponding
enable bit is cleared to 0 or if the interrupt has been masked by the CPU.
When the RES pin is driven low, system clock oscillation is started. At the same time as system
clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation settles. When the RES pin goes high after clock oscillation
settles, the CPU begins reset exception handling.
When the STBY pin is driven low, software standby mode is cancelled and a transition is made to
hardware standby mode.
Figure 28.3 shows an example in which a transition is made to software standby mode at the
falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge of the NMI pin.
Rev. 1.00 Mar. 12, 2008 Page 1069 of 1178
REJ09B0403-0100
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