Usage Notes - Renesas H8S Family Hardware Manual

26.6

1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not

the JTAG is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For

details, see section 31, Electrical Characteristics. To activate the JTAG after a reset, drive the

ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the JTAG is not

to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-impedance

state. These pins are internally pulled up and are noted in standby mode.

2. The following must be considered when the power-on reset signal is applied to the ETRST pin.

 The reset signal must be applied at power-on.

 To prevent the LSI system operation from being affected by the ETRST pin of the board

tester, circuits must be separated .

 Alternatively, to prevent the ETRST pin of the board tester from being affected by the LSI

system reset, circuits must be separated.

Figure 26.3 shows a design example of the reset signal circuit wherein no reset signal

interference occurs.

Board edge pin

System reset

Figure 26.3 Reset Signal Circuit Without Reset Signal Interference

reset circuit

Section 26 Boundary Scan (JTAG)

Rev. 1.00 Mar. 12, 2008 Page 1047 of 1178

REJ09B0403-0100