Reception Function; Data Processing Using The Receive Rule Table - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.6

Reception Function

There are two reception types.
• Reception by receive buffers:
Zero to 31 receive buffers can be shared by all channels. Since messages stored in receive buffers
are overwritten at each reception, the latest receive data can always be read.
• Reception by receive FIFO buffers and transmit/receive FIFO buffers (receive mode):
Eight receive FIFO buffers can be shared by all channels and three dedicated transmit/receive
FIFO buffers are provided for each channel. Messages of up to the number of buffer stages
specified with the RFDC[2:0] and CFDC[2:0] bits can be stored in FIFO buffers and can be read
sequentially from the oldest.
21.6.1

Data Processing Using the Receive Rule Table

Data processing using the receive rule table allows dispatching of selected messages to the specified
buffer. Data processing includes acceptance filter processing, DLC filter processing, routing
processing, label addition processing, and mirror function processing.
Up to 128 receive rules can be registered per channel and up to (64 × number of channels) total receive
rules can be registered in the entire module. (Up to 128 receive rules can be registered in this module
that has two channels.) Set receive rules for each channel. Receive rules cannot be shared with other
channels. If receive rules are not set, no messages can be received. Figure 21.6 illustrates how receive
rules are registered.
RSCAN0GAFLECTR register
0
RSCAN0GAFLID0 to RSCAN0GAFLP10 registers
1
RSCAN0GAFLID1 to RSCAN0GAFLP11 registers
2
RSCAN0GAFLID2 to RSCAN0GAFLP12 registers
3
RSCAN0GAFLID3 to RSCAN0GAFLP13 registers
4
RSCAN0GAFLID4 to RSCAN0GAFLP14 registers
5
RSCAN0GAFLID5 to RSCAN0GAFLP15 registers
6
RSCAN0GAFLID6 to RSCAN0GAFLP16 registers
7
RSCAN0GAFLID7 to RSCAN0GAFLP17 registers
8
RSCAN0GAFLID8 to RSCAN0GAFLP18 registers
9
RSCAN0GAFLID9 to RSCAN0GAFLP19 registers
10
RSCAN0GAFLID10 to RSCAN0GAFLP110 registers
11
RSCAN0GAFLID11 to RSCAN0GAFLP111 registers
12
RSCAN0GAFLID12 to RSCAN0GAFLP112 registers
13
RSCAN0GAFLID13 to RSCAN0GAFLP113 registers
14
RSCAN0GAFLID14 to RSCAN0GAFLP114 registers
15
RSCAN0GAFLID15 to RSCAN0GAFLP115 registers
RNC0[7:0], RNC1[7:0]: Bits in the RSCAN0GAFLCFG0 register
Figure 21.6
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
b8 b7 b6 b5 b4
AFL
AFLPN[4:0]
DAE
•
•
•
Note: Receive rules for each channel are set in contiguous blocks.
It is not possible to configure channel 1 rules in the block reserved for channel 0 rules.
Entry of Receive Rules (for Setting Channel 0 and 1)
b0
Receive rule table
Receive rule 0
Page 0
Page 1
Page 2
Page 3
Receive rule 60
Receive rule 0
Page 4
Page 5
Page 6
Receive rule 47
Page 7
21. CAN Interface
Channel 0 receive rules 0 to 60
61 rules (RNC0[7:0] value)
Boundary is determined by
the RNC0[7:0] bits.
Channel 1 receive rules 0 to 47
48 rules (RNC1[7:0] value)
Boundary is determined by
the RNC1[7:0] bits.
Unused receive rule area
21-126