Jtag Reset - Renesas H8S Family Hardware Manual

Section 26 Boundary Scan (JTAG)

JTAG Reset

The JTAG can be reset in two ways.

• The JTAG is reset when the ETRST pin is held at 0.

• When ETRST = 1, the JTAG can be reset by inputting at least five ETCK clock cycles while

Boundary Scan

The JTAG pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard

by setting a command in SDIR.

Supported Instructions

This LSI supports the three essential instructions defined in the IEEE1149.1 standard (BYPASS,

SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE).

BYPASS (Instruction code: B'1111)

The BYPASS instruction is an instruction that operates the bypass register. This instruction

shortens the shift path to speed up serial data transfer involving other chips on the printed circuit

board. While this instruction is being executed, the test circuit has no effect on the system

SAMPLE/PRELOAD (Instruction code: B'0100)

The SAMPLE/PRELOAD instruction inputs values from this LSI internal circuitry to the

boundary scan register, outputs values from the scan path, and loads data onto the scan path.

When this instruction is being executed, this LSI's input pin signals are transmitted directly to the

internal circuitry, and internal circuit values are directly output externally from the output pins.

This LSI system circuits are not affected by execution of this instruction.

In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal

circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the

boundary scan register and read from the scan path. Snapshot latching does not affect normal

operation of this LSI.

In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan

when the EXTEST instruction was executed an undefined value would be output from the output

Rev. 1.00 Mar. 12, 2008 Page 1044 of 1178

REJ09B0403-0100