Clock Select Circuit - Renesas H8S Family Hardware Manual

Section 27 Clock Pulse Generator
27.7

Clock Select Circuit

The clock select circuit selects the system clock that is used in this LSI.
A clock generated by the oscillator, to which the EXTAL and XTAL pins are input, and multiplied
by the PLL circuit is selected as a system clock when returning from high-speed mode, medium-
speed mode, sleep mode, the reset state, or standby mode.
Rev. 1.00 Mar. 12, 2008 Page 1055 of 1178
REJ09B0403-0100