Riicnsary - I²C Slave Address Register Y (Y = 0 To 2) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.11 RIICnSARy — I²C Slave Address Register y (y = 0 to 2)
Access: RIICnSARy is a 32-bit readable/writable register.
RIICnSARyL and RIICnSARyH are 16-bit readable/writable registers.
RIICnSARyLL, RIICnSARyLH, RIICnSARyHL, and RIICnSARyHH are 8-bit readable/writable registers.
Address: RIICnSAR0: <RIICn_base> + 0028
RIICnSAR0L: <RIICn_base> + 0028
RIICnSAR0LL: <RIICn_base> + 0028
RIICnSAR0HH: <RIICn_base> + 002B
RIICnSAR1: <RIICn_base> + 002C
RIICnSAR1L: <RIICn_base> + 002C
RIICnSAR1LL: <RIICn_base> + 002C
RIICnSAR1HH: <RIICn_base> + 002F
RIICnSAR2: <RIICn_base> + 0030
RIICnSAR2L: <RIICn_base> + 0030
RIICnSAR2LL: <RIICn_base> + 0030
RIICnSAR2HH: <RIICn_base> + 0033
Initial Value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
FSy — —
0 0 0
Initial value
R/W R/W R R
Table 18.17
Bit Position
31 to 16
15
14 to 10
9 to 1
0
SVA0 Bit (10-Bit Address LSB)
When the 10-bit address format is selected (RIICnSARy.FSy = 1), this bit functions as the LSB of a 10-
bit address and forms a 10-bit address in combination with the SVA[9:1] bits.
When the RIICnSER.SARy bit is set to 1 (RIICnSARy enabled) and the RIICnSARy.FSy bit is 1, this
bit is valid. While the RIICnSARy.FSy bit or SARy bit is 0, the setting of this bit is ignored.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnSAR0H: <RIICn_base> + 002A
H
, RIICnSAR0LH: <RIICn_base> + 0029
H
H
H
, RIICnSAR1H: <RIICn_base> + 002E
H
, RIICnSAR1LH: <RIICn_base> + 002D
H
H
H
, RIICnSAR2H: <RIICn_base> + 0032
H
, RIICnSAR2LH: <RIICn_base> + 0031
H
H
This register is initialized by any reset.
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R R/W
RIICnSARy register contents
Bit Name Function
― Reserved
These bits are read as 0. The write value should be 0.
FSy 7-Bit/10-Bit Address Format Selection
0: The 7-bit address format is selected.
1: The 10-bit address format is selected.
― Reserved
These bits are read as 0. The write value should be 0.
SVA[9:1] 7-Bit Address/10-Bit Address Upper Bits
A slave address is set.
• When the FSy bit is 0 (7-bit address format), the SVA[7:1] bits are Valid and
• When the FSy bit is 1 (10-bit address format), SVA[9:1] bits form a 10-bit
SVA0 10-Bit Address LSB
The least significant bit (LSB) of a 10-bit slave address is set.
• When the FSy bit is 0 (7-bit address format), this bit is invalid.
• When the FSy bit is 1 (10-bit address format), this bit is a 10-bit slave
H
H
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
0 0 0 0
R/W R/W R/W
form a 7-bit slave address.
slave address (combined with the SVA0 bit).
address (combined with the SVA[9:1] bits).
18. I²C Bus Interface
, RIICnSAR0HL: <RIICn_base> + 002A
H
, RIICnSAR1HL: <RIICn_base> + 002E
H
, RIICnSAR2HL: <RIICn_base> + 0032
H
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
SVA[9:1]
0 0 0 0
R/W R/W R/W R/W
,
H
,
H
,
H
17 16
— —
0 0
R R
1 0
SVA0
0 0
R/W R/W
18-35