Slave Address Register (Sar); C Bus Transmit Data Register (Icdrt); C Bus Receive Data Register (Icdrr); C Bus Shift Register (Icdrs) - Renesas H8S/2368 Series Hardware Manual

15.3.6

Slave Address Register (SAR)

SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode,
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device.
Bit Bit Name Initial Value R/W
7 to SVA6 to 0
1
SVA0

0 0
2
15.3.7 I

C Bus Transmit Data Register (ICDRT)

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
2
space in the I C bus shift register (ICDRS), it transfers the transmit data which is written in
ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible.
2
15.3.8 I

C Bus Receive Data Register (ICDRR)

ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the received data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot be written to this register.
2
15.3.9 I

C Bus Shift Register (ICDRS)

ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read from the CPU.
Description
R/W Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I
R/W Reserved
Though this bit can be read from or written to, the write
value should always be 0.
2
C bus.
Rev. 2.00, 05/03, page 601 of 820