Second Slave Address Register (Sarx) - Renesas H8S/2633 Series Hardware Manual

DDCSWR SAR
Bit 6 Bit 0
SW FS
0 0
1
1 —
18.2.3

Second Slave Address Register (SARX)

Bit : 7
SVAX6
Initial value : 0
R/W : R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to
SVAX0, differing from the addresses of other slave devices connected to the I
808
SARX
Bit 0
FSX Operating Mode
2
0 I C bus format
•
SAR and SARX slave addresses recognized
2
1 I C bus format
•
SAR slave address recognized
•
SARX slave address ignored
2
0 I C bus format
•
SAR slave address ignored
•
SARX slave address recognized
1 Synchronous serial format
•
SAR and SARX slave addresses ignored
— Must not be set.
6 5
SVAX5 SVAX4
0 0
R/W R/W
4 3
SVAX3 SVAX2 SVAX1
0 0
R/W R/W R/W
(Initial value)
2 1 0
SVAX0 FSX
0 0 1
R/W R/W
2
C bus.