Second Slave Address Register (Sarx); Table 17.2 Communication Format - Renesas H8S/2158 User Manual

17.3.3

Second Slave Address Register (SARX)

SARX sets the second slave address and selects the communication format. In slave mode,
transmit/receive operations by the DTC are possible when the received address matches the
second slave address. When the LSI is in slave mode with the I
7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI
operates as the slave device specified by the master device. SARX can be accessed only when the
ICE bit in ICCR is cleared to 0.
Bit Bit Name Initial Value R/W
7 SVAX6 0
6 SVAX5 0
5 SVAX4 0
4 SVAX3 0
3 SVAX2 0
2 SVAX1 0
1 SVAX0 0
0 FSX 1

Table 17.2 Communication Format

SAR SARX
FS FSX
0 0
0 1
1 0
1 1
Description
R/W Second Slave Address 6 to 0
R/W Set the second slave address.
R/W
R/W
R/W
R/W
R/W
R/W Format Select X
Selects the communication format together with the FS
bit in SAR. For details, see table 17.2.
Communication Format
SAR and SARX are used as the slave addresses with the I
format.
Only SAR is used as the slave address with the I
Only SARX is used as the slave address with the I
Clocked synchronous serial format (SAR and SARX are invalid)
2
Section 17 I C Bus Interface (IIC)
2
C bus format selected, if the upper
2
C bus format.
2
Rev. 3.00 Jan 25, 2006 page 481 of 872
2
C bus
C bus format.
REJ09B0286-0300