Second Slave Address Register (Sarx) - Renesas H8S/2100 Series Hardware Manual

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Section 17 I C Bus Interface (IIC)
17.3.3

Second Slave Address Register (SARX)

SARX sets the second slave address and selects the communication format. If the LSI is in slave
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mode with the I C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX
match the upper 7 bits of the first frame received after a start condition, the LSI operates as the
slave device specified by the master device. SARX can be accessed only when the ICE bit in
ICCR is cleared to 0.
Bit Bit Name
7 SVAX6
6 SVAX5
5 SVAX4
4 SVAX3
3 SVAX2
2 SVAX1
1 SVAX0
0 FSX
Rev. 1.00 May 09, 2008 Page 498 of 954
REJ09B0462-0100
Initial
Value R/W Description
0 R/W Second Slave Address 6 to 0
0 R/W Set the second slave address.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W Format Select X
Selects the communication format together with the FS
bit in SAR. See table 17.3.