Section 5 Exception Handling; Summary Of Exception Handling; Register Descriptions - Renesas SH7781 Hardware Manual

5.1

Summary of Exception Handling

Exception handling processing is handled by a special routine which is executed by a reset,
general exception handling, or interrupt. For example, if the executing instruction ends
abnormally, appropriate action must be taken in order to return to the original program sequence,
or report the abnormality before terminating the processing. The process of generating an
exception handling request in response to abnormal termination, and passing control to a user-
written exception handling routine, in order to support such functions, is given the generic name of
exception handling.
The exception handling in this LSI is of three kinds: resets, general exceptions, and interrupts.
5.2

Register Descriptions

Table 5.1 lists the configuration of registers related exception handling.
Table 5.1 Register Configuration
Register Name
TRAPA exception register
Exception event register
Interrupt event register
Non-support detection exception
register
Note: * P4 is the address when virtual address space P4 area is used. Area 7 is the address
when physical address space area 7 is accessed by using the TLB.

Section 5 Exception Handling

Abbr. R/W
TRA R/W
EXPEVT R/W
INTEVT R/W
EXPMASK R/W
Area 7
P4 Address* Address*
H'FF00 0020 H'1F00 0020
H'FF00 0024 H'1F00 0024
H'FF00 0028 H'1F00 0028
H'FF2F 0004 H'1F2F 0004
Rev.1.00 Jan. 10, 2008 Page 89 of 1658
5. Exception Handling
Access Size
32
32
32
32
REJ09B0261-0100