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M16C/29 Group
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to "0" by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing "0000
the TAZIE bit in ONSF register to "1" (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit of INT2IC register. The Z-phase pulse width
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.1.2.1.1
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
TA3
OUT
(A phase)
TA3
IN
(B phase)
Count source
(Note)
INT2
(Z phase)
Timer A3
Note: This timing diagram is for the case where the POL bit of INT2IC register = "1" (= rising edge).
Figure 12.1.2.1.1. Two-phase Pulse (A phase and B phase) and the Z Phase
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
_______
m
page 103 of 402
Input equal to or greater than one clock cycle
of count source
m+1
1
2
_______
" to the TA3 register and setting
16
3
4
5
12.1 Timer A
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