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Section 28 Power-Down Modes
28.7
Module Stop Mode
Module stop mode can be individually set for each on-chip peripheral module.
When the corresponding MSTP bit in MSTPCR and SUBMSTP is set to 1, module operation
stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the
corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation
resumes at the end of the bus cycle. In module stop mode, the internal states of on-chip peripheral
modules other than the PWMX, A/D converter, and part of the SCI are retained.
After the reset state is cancelled, all modules other than DTC are in module stop mode.
While an on-chip peripheral module is in module stop mode, read/write access to its registers is
disabled.
28.8
Usage Notes
28.8.1
I/O Port Status
The status of the I/O ports is retained in software standby mode. Therefore, when a high level is
output, the current consumption is not reduced by the amount of current to support the high level
output.
28.8.2
Current Consumption when Waiting for Oscillation Settling
The current consumption increases during oscillation settling.
28.8.3
DTC Module Stop Mode
If the DTC module stop mode specification and DTC bus request occur simultaneously, the bus is
released to the DTC and the MSTP bit cannot be set to 1. After completing the DTC bus cycle, set
the MSTP bit to 1 again.
28.8.4
Notes on Subclock Usage
When using the subclock, make a transition to power-down mode after setting the EXCLE bit in
LPWRCR to 1 and loading the subclock two or more cycles. When not using the subclock, the
EXCLE bit should not be set to 1.
Rev. 1.00 Mar. 12, 2008 Page 1072 of 1178
REJ09B0403-0100
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