Freescale Semiconductor MPC8313E Family Reference Manual page 1141

Table 18-14 describes the ULCR fields.
Bits Name
0 DLAB Divisor latch access bit
0 Access to all registers except UDLB, UAFR, and UDMB.
1 Ability to access UDMB, UDLB, and UAFR.
1 SB Set break
0 Send normal UTHR data onto the SOUT signal.
1 Force logic 0 to be on SOUT. Data in the UTHR is not affected.
2 SP Stick parity
0 Stick parity is disabled.
1 If PEN = 1 and EPS = 1, space parity is selected; if PEN = 1 and EPS = 0, mark parity is selected.
3 EPS Even parity select. See
0 If PEN = 1 and SP = 0 then odd parity is selected.
1 If PEN = 1 and SP = 0 then even parity is selected.
4 PEN Parity enable
0 No parity generation and checking.
1 Generate parity bit as a transmitter, and check parity as a receiver.
5 NTSB Number of STOP bits
0 One STOP bit is generated in the transmitted data.
1 When a 5-bit data length is selected, 1 1/2 STOP bits are generated. When either a 6-, 7-, or 8-bit word
length is selected, two STOP bits are generated.
6–7 WLS Word length select. Number of bits that comprise the character length.
00 5 bits
01 6 bits
10 7 bits
11 8 bits
Table 18-15. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS]
PEN
0
0
0
0
1
1
1
1
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 18-14. ULCR Field Descriptions
Description
Table 18-15.
SP EPS
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Parity Selected
No parity
No parity
No parity
No parity
Odd parity
Even parity
Mark parity
Space parity
DUART
18-13