Freescale Semiconductor MPC8313E Family Reference Manual page 1108

2
I C Interfaces
function is performed on both of these signals with external pull-up resistors. Refer to the hardware
specifications for electrical characteristics.
Table 17-2. I
Signal I/O
SCL1, I/O Serial clock. Performs as an input when the device is programmed as an I
SCL2 an output when the device is programmed as an I
O As outputs for the bidirectional serial clock, these signals operate as described below.
State
Meaning
I As inputs for the bi-directional serial clock, these signals operate as described below.
State
Meaning
SDA1, I/O Serial data. Performs as an input when the device is in a receiving mode. SDA n also performs as an output
SDA2 signal when the device is transmitting (as an I
O As outputs for the bi-directional serial data, these signals operate as described below.
State
Meaning
I As inputs for the bi-directional serial data, these signals operate as described below.
State
Meaning
2
17.3 I C Memory Map/Register Definition
2
Table 17-3 lists the I C–specific registers and their addresses.
Address
0x0_3000 I2C1ADR—I
0x0_3004 I2C1FDR—I
0x0_3008 I2C1CR—I
0x0_300C I2C1SR—I
0x0_3010 I2C1DR—I
0x0_3014 I2C1DFSRR—I
0x0_301C– Reserved, should be cleared
0x0_30FF
0x0_3100 I2C2ADR—I
0x0_3104 I2C2FDR—I
0x0_3108 I2C2CR—I
0x0_310C I2C2SR—I
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
17-4
2
C Interface Signals—Detailed Signal Descriptions
Asserted/Negated—Driven along with SDA n as the clock for the data.
2
Asserted/Negated—The I C unit uses this signal to synchronize incoming data on SDA n . The bus
is assumed to be busy when this signal is detected low.
Asserted/Negated—Data is driven.
Asserted/Negated—Used to receive data from other devices. The bus is assumed to be busy when
SDA n is detected low.
Table 17-3. I
2
I C Register
2
C1 address register
2
C1 frequency divider register
2
C1 control register
2
C1 status register
2
C1 data register
2
C1 digital filter sampling rate register
2
C2 address register
2
C2 frequency divider register
2
C2 control register
2
C2 status register
Description
2
C master.
2
C master or a slave).
2
C Memory Map
Access
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
2
C slave. SCL n also performs as
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