Freescale Semiconductor MPC8313E Family Reference Manual page 1249

15.5.3.6.6, 15-73
15.5.3.7.19, 15-89
15.5.3.7.25, 15-92
15.5.3.9, 15-107
15.6.2.10.3, 15-157
15.6.5.2, 15-170
15.6.6.2, 15-178
115.6.6.3, 15-182
15.7.1.5, 15-199
Chapter 16
16.1, 16-1
16.1, 16-2
16.2, 16-3
16.2.2, 16-4
16.3, 16-7
16.3.1.6, 16-11
16.3.2.13, 16.25
16.3.2.13, 16-27
16.3.2.27, 16-41
16.10, 16-155
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
"Maximum Receive Buffer length Register (MRBLR)," and Section 15.6.6.3,
"Receive Buffer Descriptors (RXBD)."
Added a note regarding eTSEC system clock to MgmtClk bit description.
Modified RCSE bit description.
In Table 15-86, added the following note to TBYT[TBYT]:
The value of TBYT may be greater than the actual number of bytes transmitted if
the frame is truncated because it exceeds MAXFRM.
Removed text related to L2 cache.
In Table 15-149, "Interrupt Coalescing Timing Threshold Ranges,
eTSEC frequencies of 266 and 333 MHz with 133 and 166 MHz
information/rows.
Modified Figure 15-145 and changed the name from 'Alcatel MAC' to 'Ethernet
MAC.'
In Table 15-164, modified bit TR to clarify when truncation occurs on transmit.
In Table 15-165, corrected description of RxBD TR (truncation) field to state that
TR can also be set if a frame length equal to the maximum frame length is
received. Modified descriptions of bit LG.
In Table 15-178, changed SerDes and SGMII signal frequency from 625 MHz to
1250 MHz, TXD and RXD to TXDp/TXDn and RXDp/RXDn, respectively.
Throughout this chapter changed references from endpoint 5 to endpoint 2 and
removed offsets for endpoints 3, 4, and 5.
Changed 'Access in Memory Map' to match register figure; USBSTS, PORTSC,
OTGSC, ENDRPT Complete, and ENDPTCTRL. In figure, changed access to
'Mixed from R/W,' in memory map, changed reset values to match register
figures: USBCMD, FRIDEX, and PERIODICLISTBASE.
In Figure 16-1, updated diagram.
Table 16-1: removed mentioning of UTMI signals, as they are internal signals;
added UTMI PHY external signals.
Removed the note, 'The ULPI signals are multiplexed with UTMI interface.'
Removed ENDPTCTRL3–5 registers.
In Figure 16-7, changed DEN reset value to 0011.
Corrected bit description by switching PORTSC[LS] bit 01 (J-state) with 10
(K-state). Also modified the order to 00,10,01,11.
In Table 16-22, for bits 11-10, modified the order of 00,01,10,11 to 00,10,01,11.
Changed PORTSC[PTX] to 'Reserved.'
In Table 16-36, added the following note for bits 30 and 31: 'PORTSC[PHCD] bit
must be set.' Also for RefSel[1:0] changed bits 01 to 24 MHz instead of 16 MHz
and changed 00 to 'Reserved' instead of 12 MHz.
In Table 16-98, replaced all TBDs with actual values.
Revision History
replaced
"
A-71