Freescale Semiconductor MPC8313E Family Reference Manual page 1243

17.3.1.5, 17-9
17.5.5, 17-22
18.3.1.3, 18-7
18.3.1.3, 18-8
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Deleted Table 16-63 and renumbered the rest of the tables in the chapter.
Table 17-8, changed the last sentence in the DATA description to read:
Note that in both master receive and slave receive modes, the very first read is
always a dummy read.
In second paragraph, removed the sentence: 'For 1-byte transfers, a dummy read
should be performed by the interrupt service routine (see Figure 17-11).'
In Table 18-8, replaced the table with 133 and 167 MHz information.
In the last paragraph, changed item 1 as follows:
1. The input clock frequency (ICF) is divided by the actual frequency input (AFI)
to get the correct divisor value (ICF/AFI, where AFI = baud
rate × 16 × divisor).
Revision History
A-65