Freescale Semiconductor MPC8313E Family Reference Manual page 1018

Powerquicc ii pro integrated processor
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Universal Serial Bus Interface
1-millisecond boundaries is called H-Frames. The high-speed bus's view of the 1-millisecond boundaries
is called B-Frames.
HC Periodic
Schedule
7
0
Micro-Frames
SS
HS Bus
Frames
Figure 16-46. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries
H-Frame boundaries for the host controller correspond to increments of FRINDEX[13–3]. Microframe
numbers for the H-Frame are tracked by FRINDEX[2–0]. B-Frame boundaries are visible on the
high-speed bus via changes in the SOF token's frame number. Microframe numbers on the high-speed bus
are only derived from the SOF token's frame number (that is, the high-speed bus will see eight SOFs with
the same frame number value). H-Frames and B-Frames have the fixed relationship (that is, B-Frames lag
H-Frames by one microframe time) illustrated in
naturally aligned to H-Frames. Software schedules transactions for full- and low-speed periodic endpoints
relative the H-Frames. The result is these transactions execute on the high-speed bus at exactly the right
time for the USB 2.0 hub periodic pipeline. As described in
(FRINDEX),"
the SOF Value can be implemented as a shadow register (in this example, called SOFV),
which lags the FRINDEX register bits [13–3] by one microframe count.
required relationship between the value of FRINDEX and the value of SOFV. This lag behavior can be
accomplished by incrementing FRINDEX[13–3] based on carry-out on the 7 to 0 increment of
FRINDEX[2–0] and incrementing SOFV based on the transition of 0 to 1 of FRINDEX[2–0].
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-76
HC Periodic Schedule
Frame Boundaries
1
2
3
4
5
CS
CS
CS
CS
Full/Low-Speed
Transaction
B-Frame N
H-Frame N
Interface Data Structure
HS/FS/LS Bus
Frame Boundaries
6
7
0
1
2
3
SS
CS
CS
Full/Low-Speed
Transaction
H-Frame N+1
Interface Data Structure
Figure
16-46. The host controller's periodic schedule is
Section 16.3.2.4, "Frame Index Register
4
5
6
7
0
CS
CS
B-Frame N+1
Table 16-65
illustrates the
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