Freescale Semiconductor MPC8313E Family Reference Manual page 1237

TX BD Ring
Data Buffer Length=8
Data Buffer Pointer
Data Buffer Length=M
Data Buffer Pointer
Figure 15-73. Figure 15-142. Buffer Format for Transmit Time-Stamp Insertion
15.6.6.5.2 15.6.6.5.2Error Condition
When an error is encountered after a PTP packet has begun to be processed, the timestamp written to the
TxPAL is zero. Subsequent frames may be flushed by eTSEC. There will be no timestamp update to
TxPAL for the subsequent flushed frames.
15.6.6.6 15.6.6.6Tx PTP Packet Parsing
Software instructs the Tx packet to be timestamped via setting bit 15 in the TxFCB to mark a PTP packet.
TxFCB[VLCTL] can be translated as the Tx PTP packet identification number. BD[TOE] must be set to
enable transmit PTP packet time stamping. TxFCB[PTP] bit takes precedence over TxFCB[VLN] bit. It
disables per packet VLAN tag insertion. On a PTP packet, a VLAN tag can be inserted from the DFVLAN
register. The TxFCB for the PTP packet is shown in Figure 15-143.
0
Offset + 0 VLN
Offset + 2
Offset + 4
Offset + 6
The contents of the Tx FCB are defined in Table 15-160.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
TOE=1
1 2 3 4 5
IP IP6 TUP UDP CIP CTU NPH
L4OS
Figure 15-143. Transmit Frame Control Block
External Memory
32B cache-lines
0 1 2
FCB
8 Bytes
6 7 8 9 10
PHCS
VLCTL/PTP_ID
Revision History
3 ... 7
TxFCB
TxPAL
TxPAL
TxPAL
Unknown
Unknown
FRAME
11 12 13 14
PTP
L3OS
15
A-59