Freescale Semiconductor MPC8313E Family Reference Manual page 1191

10.4.1.6, 10-45
When the FCM is in the middle of a long transaction (such as NAND erase,
write, and so on), another transaction on the GPCM or UPM will trigger the
bus monitor to start, even though the GPCM or UPM is waiting for the FCM
to finish. If the bus monitor times out, it could corrupt the current NAND
Flash operation as well as terminate the GPCM or UPM operation. To avoid
such cases, it is recommended that the bus monitor timeout be programmed
to its maximum setting of LBCR[BMT] = 0 and LBCR[BMTPS] = 0xF.
10.4.2.4, 10-56
LCLK
Address
LAD
LALE
A
TA
LGTA
LCS n
LBCTL
LOE
10.4.4.4.7, 10-85
Multiple-bank DRAM and SDRAM devices require that the bank address
be driven during both RAS and CAS cycles. The UPM does not support a
persistent bank address on both RAS and CAS cycles. Therefore, external
logic must be used to supply a bank address to these devices.
10.4.4.5, 10-87
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Add the following note at the end of the section:
Replace Figure 10-43, "External Termination of GPCM Access," with the
following figure for devices without PLL:
Latched Address
Add the following note prior to Table 10-42, "UPM Address Multiplexing:"
Remove the section, "Synchronous Sampling of LUPWAIT for Early Transfer
Acknowledge," occurring after Section 10.4.4.4.10, "Wait Mechanism (WAEN),"
from devices that do not support PLL. Subsequent sections are re-numbered.
NOTE
1st 2nd
Sample Sample
Point Point
Read Data
NOTE
Revision History
A-13