Freescale Semiconductor MPC8313E Family Reference Manual page 1182

Revision History
4.5.2.3, 4-40
5.2.4.4.1, 5-9
RCWHR[RLEXT]/
RCWHR[ROMLOC]
00 / 000–100
00 / 101–111
5.2.4.6.1, 5-11
RCWHR[RLEXT]/RC PCILAWR0[EN]
WHR[ROMLOC]
00 /000, 011–111
01–11 / 000–111
00 / 001
5.2.4.8.1, 5-14
RCWHR[RLEXT]/
RCWHR[ROMLOC]
00 / 000
Else
5.3.2.6, 5-24
5.3.2.9, 5-29
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-4
In Table 4-36, "SCCR Bit Descriptions," update bit field description of ENCCM:
"Encryption core, JTAG, and I
00 Encryption core clock is disabled.
01 Encryption core clock/csb_clk ratio is 1:1.
10 Encryption core clock/csb_clk ratio is 1:2 (csb_clk has higher frequency
than the encryption core).
11 Encryption core clock/csb_clk ratio is 1:3 (csb_clk has higher frequency
than the encryption core).
Note: The encryption core must have the same clock ratio as the USB unit, unless
one of them has its clock disabled."
In Table 5-10, "LBLAWAR0[EN] Reset Value," add the RCWHR[RLEXT] value
in the RCWHR[ROMLOC] column as follows:
LBLAWAR0[EN]
Reset Value
0 e300c3 core boot not performed from a local bus device.
1 e300c3 core boot performed from a local bus device. Local bus 8-Mbyte
(22+1)
(2
In Table 5-14, "PCILAWAR0[EN] Reset Value," add the RCWHR[RLEXT] value
in the RCWHR[ROMLOC] column.
Reset Value
0 e300c3 core boot not performed from a PCI device.
0 e300c3 core boot not performed from a PCI device.
1 e300c3 core boot performed from a PCI device. PCI 8-Mbyte (2
access window is enabled.
In Table 5-18, "DDRLAWAR0[EN] Reset Value," add the RCWHR[RLEXT]
value in the RCWHR[ROMLOC] column.
DDRLAWAR0[EN]
Reset Value
1 e300c3 core boot performed from a DDR SDRAM device. DDR 8-Mbyte
(22+1)
(2
0 e300c3 core boot not performed from a DDR SDRAM device.
In second paragraph, change "A value of 0b11 is illegal for all groups.," to "A
value of 0b11 selects GPIO mode of the appropriate pin."
In Figure 5-17, "DDR Debug Status Register (DDRDSR)," make register bits
read-only, as according to register access.
2
C1 clock mode.
Description
) local access window is enabled.
Description
Description
) local access window is enabled.
(22+1)
) local
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