Freescale Semiconductor MPC8313E Family Reference Manual page 1174

General Purpose I/O (GPIO)
• Open-drain capability on all ports
• All ports can optionally generate an interrupt upon changing their state.
21.2 External Signal Description
The following section provides information about GPIO signals.
21.2.1 Signals Overview
Table 21-1 provides detailed descriptions of the external GPIO signals.
Table 21-1. GPIO External Signals—Detailed Signal Descriptions
Signal I/O
GPIO[0:31] I/O General purpose I/O. Each signal can be set individually to act as input or output, according to application
needs.
State
Meaning
Timing Assertion/Negation—Inputs can be asserted completely asynchronously.
21.3 Memory Map/Register Definition
The GPIO has programmable registers that occupy 24 bytes of memory-mapped space. Note that reading
undefined portions of the memory map returns all zeros and writing has no effect.
All GPIO registers are 32 bits wide and are located on 32-bit address boundaries. All addresses used in this
chapter are offsets from the address held in IMMRBAR as defined in
Table 21-2 shows the memory map of GPIO.
Offset
0xC00 GPIO direction register (GPDIR)
0xC04 GPIO open drain register (GPODR)
0xC08 GPIO data register (GPDAT)
0xC0C GPIO interrupt event register (GPIER)
0xC10 GPIO interrupt mask register (GPIMR)
0xC14 GPIO external interrupt control register (GPICR)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
21-2
Asserted/Negated—Defined per application.
Outputs are asynchronous to any externally visible clock
Table 21-2. GPIO Register Address Map
Register
Description
Chapter 2, "Memory Map."
Access Reset Value
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
w1c
R/W 0x0000_0000
R/W 0x0000_0000
Section/Page
21.3.1/21-3
21.3.2/21-3
21.3.3/21-4
Undefined 21.3.4/21-4
21.3.5/21-4
21.3.6/21-5
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