Freescale Semiconductor MPC8313E Family Reference Manual page 1051

Powerquicc ii pro integrated processor
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transaction spans more than one location in the periodic list.(for example, it takes two siTDs in
adjacent periodic frame list locations to fully describe the scheduling for the split transaction).
Although the scheduling of the split transaction may take two data structures, all of the
complete-splits for each full-speed IN isochronous transaction must use only one data pointer. For
this reason, siTDs contain a back pointer.
Software must never schedule full-speed isochronous OUTs across an H-Frame boundary.
Case 2b: This case can only occur for a very large isochronous IN. It is the only allowed scenario
where a start-split and complete-split for the same endpoint can occur in the same microframe.
Software must enforce this rule by scheduling the large transaction first. Large is defined to be
anything larger than 579 byte maximum packet size.
A subset of the same mechanisms employed by full- and low-speed interrupt queue heads are employed
in siTDs to schedule and track the portions of isochronous split transactions. The following fields are
initialized by system software to instruct the host controller when to execute portions of the split
transaction protocol:
SplitXState
This is a single bit residing in the Status field of an siTD (see
the current state of the split transaction. The rules for managing this bit are described in
Section 16.6.12.3.3, "Split Transaction Execution State Machine for Isochronous."
Frame S-mask
This is a bit-field wherein system software sets a bit corresponding to the microframe (within an
H-Frame) that the host controller should execute a start-split transaction. This is always qualified
by the value of the SplitXState bit. For example, referring to the IN example in
1, the S-mask would have a value of 0b0000_0001 indicating that if the siTD is traversed by the
host controller, and the SplitXState indicates Do Start Split, and the current microframe as
indicated by FRINDEX[2–0] is 0, then execute a start-split transaction.
Frame C-mask
This is a bit-field where system software sets one or more bits corresponding to the microframes
(within an H-Frame) that the host controller should execute complete-split transactions. The
interpretation of this field is always qualified by the value of the SplitXState bit. For example,
referring to the IN example in
0011_1100 indicating that if the siTD is traversed by the host controller, and the SplitXState
indicates Do Complete Split, and the current microframe as indicated by FRINDEX[2–0] is 2, 3,
4, or 5, then execute a complete-split transaction.
Back Pointer
This field in a siTD is used to complete an IN split-transaction using the previous H-Frame's siTD.
This is only used when the scheduling of the complete-splits span an H-Frame boundary.
There exists a one-to-one relationship between a high-speed isochronous split transaction (including all
start- and complete-splits) and one full-speed isochronous transaction. An siTD contains (amongst other
things) buffer state and split transaction scheduling information. An siTD's buffer state always maps to one
full-speed isochronous data payload. This means that for any full-speed transaction payload, a single
siTD's data buffer must be used. This rule applies to both IN an OUTs. An siTD's scheduling information
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure
16-57, case 1, the C-mask would have a value of 0b
Universal Serial Bus Interface
Table
16-49). This bit is used to track
Figure
16-57, case
16-109

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