Freescale Semiconductor MPC8313E Family Reference Manual page 1221

5.7.2, 5-50
5.7.6.1, 5-62
5.8.1, 5-65
5.8.3.2, 5-67
31 PMCI Power management controller interrupt.
When set, indicates that one of the following events has occurred:
• One of the unmasked wake-up events (bits 23–30) occurred and PMCCR1[PME_vPEN] is cleared, or
• PM current state (as indicated in PMCCR1[CURR_STATE]) is different than PM next state (as written to
PCIPMR1[Power_State] and indicated in PMCCR1[NEXT_STATE]) and PMCCR1[USE_STATE] is set,
or
• CSB platform is in low power mode and a new CSB bus request is detected
If PMCMR[PMCIE] is set, the PMC interrupt request to the PowerPC core is driven, causing the PowerPC
core to exit its low power state. PMCI can be cleared by writing a 1 to it (writing zero has no effect).
5.8.3.4, 5-70
5.8.3.7.1, 5-79
5.8.3.7.2, 5-84
5.8.3.7.3, 5-88
6.2.1, 6-2
8.4.2, 8-6
9.4.1.2, 9-10
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Changed the 5th thru 8th bullets to read:
•Maximum period of ~412.3 seconds (at 167-MHz bus clock and prescaler = 256)
for 16-bit timer
•Maximum period of ~825 seconds (at 167-MHz bus clock and prescaler = 256)
for 32-bit timer
•Maximum period of thousands of years (at 167-MHz bus clock and prescaler =
256) for 64-bit timer
•3-nanosecond timer resolution (at 167-MHz bus clock and no prescaler)
•Resolution and maximum period can be traded off by selecting prescaler divisor
In the third paragraph, changed the last sentence to read:
The maximum period (when the reference value is all ones and the prescaler
divides by 256) for one 16-bit timer is ~50 ms at 333 MHz.
Deleted the section number and title only and renumbered the remaining sections.
In Table 5-67, bits 23–30, added the following footnote to each bit description:
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR
is cleared.
Table 5-67, bit 31, changed the description to the following:
In Figure 5-54, changed the bit field 'NEXT_STATE' to read only.
In the text box of Figure 5-57, changed 'Uninitialized' to 'Not Initialized'.
In note 6, changed the Word 'uninitialized' to 'non-initialized'.
In the Notes, changed the second note 3 to 4 and renumbered the rest of the notes.
Added the initial two steps.
In Figure 5-58, changed the signal name 'PWR_EN' to 'EXT_PWR_CTRL'.
In Figure 5-59, changed the signal name 'PWR_EN' to 'EXT_PWR_CTRL'.
In Table 6-2, reserved fields changed from "Write reserved, read = 0" to
"Reserved, write should preserve reset value."
In table 8-2, signal IRQ[0:40:7], in the Description column (State Meaning),
changed the first sentence to read:
When an external interrupt request signal is asserted, the priority is checked by the
IPIC unit, and the interrupt is conditionally passed to the processor.
In Table 9-7, Bits 9–11 row, changed 011–111 Reserved to 011 Reserved.
Revision History
A-43