Freescale Semiconductor MPC8313E Family Reference Manual page 1074

Universal Serial Bus Interface
3. Set the CONTROL[CLKIN_SEL] bits to select the source and divider of the UTMI reference
clock.
4. Set the CONTROL[PHY_CLK_SEL] bits to select the UTMI PHY as the source of USB controller
PHY clock.
5. Set the CONTROL[UTMI_PHY_EN] to enable the UTMI PHY and release the PLL.
6. Wait for the PHY clock to become valid. This can be determined by polling the
CONTROL[PHY_CLK_VALID] status bit.
Once the PHY clock is valid the user can proceed to the host controller initialization phase.
To configure the external ULPI PHY the following initialization sequence is required.
1. After power-on reset the UTMI PHY will be in disabled state and the PLL will be held reset. The
UTMI PHY should remain disabled if the ULPI is being used.
2. Set the CONTROL[PHY_CLK_SEL] bits to select the ULPI PHY as the source of USB controller
PHY clock.
3. Wait for PHY clock to become valid. This can be determined by polling the
CONTROL[PHY_CLK_VALID] status bit. Note that this bit is not valid once the
CONTROL[USB_EN] bit is set.
Once the PHY clock is valid the user can proceed to the device controller initialization phase.
In order to initialize a device, the software should perform the following steps:
1. Set the controller mode to device mode. Optionally set USBMODE[SDIS] (streaming disable).
Transitioning from host mode to device mode requires a device controller
reset before modifying USBMODE.
2. Optionally modify the BURSTSIZE register.
3. Program PORTSC[PTS] if using a non-ULPI PHY.
4. Set CONTROL[USB_EN]
5. Allocate and initialize device queue heads in system memory Minimum: Initialize device queue
heads 0 Tx and 0 Rx.
All device queue heads must be initialized for control endpoints before the
endpoint is enabled. Device queue heads for non-control endpoints must be
initialized before the endpoint can be used.
For information on device queue heads, refer
6. Configure the ENDPOINTLISTADDR pointer.
For additional information on ENDPOINTLISTADDR, refer to the register table.
7. Enable the microprocessor interrupt associated with the USB DR module and optionally change
setting of USBCMD[ITC].
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-132
NOTE
NOTE
toSection 16.7, "Device Data Structures."
Freescale Semiconductor