Freescale Semiconductor MPC8313E Family Reference Manual page 1143

Table 18-17 describes the ULSR fields.
Bits Name
0 RFE Receiver FIFO error.
0 Cleared when there are no errors in the receiver FIFO or on a read of the ULSR with no remaining receiver
FIFO errors.
1 Set when one of the characters in the receiver FIFO encounters an error (framing, parity, or break
interrupt).
1 TEMT Transmitter empty
0 Either or both the UTHR or the internal transmitter shift register has a data character. In FIFO mode, a data
character is in the transmitter FIFO or the internal transmitter shift register.
1 Both the UTHR and the internal transmitter shift register are empty. In FIFO mode, both the transmitter
FIFO and the internal transmitter shift register are empty.
2 THRE Transmitter holding register empty
0 UTHR is not empty.
1 A data character has transferred from the UTHR into the internal transmitter shift register. In FIFO mode,
the transmitter FIFO contains no data character.
3 BI Break interrupt
0 Cleared when the ULSR is read or when a valid data transfer is detected (that is, STOP bit is received).
1 Received data of logic 0 for more than START bit + Data bits + Parity bit + one STOP bits length of time.
A new character is not loaded until SIN returns to the mark state (logic 1) and a valid START is detected.
In FIFO mode, a zero character is encountered in the FIFO (the zero character is at the top of the FIFO).
In FIFO mode, only one zero character is stored.
4 FE Framing error
0 Cleared when ULSR is read or when a new character is loaded into the URBR from the receiver shift
register.
1 Invalid STOP bit for receive data (only the first STOP bit is checked). In FIFO mode, FE is set when the
character that detected a framing error is encountered in the FIFO (that is the character at the top of the
FIFO). An attempt to resynchronize occurs after a framing error. The UART assumes that the framing error
(due to a logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP bit overlapping with
the next START bit, so it assumes this logic 0 sample is a true START bit and then will receive the following
new data.
5 PE Parity error
0 Cleared when ULSR is read or when a new character is loaded into URBR.
1 Unexpected parity value encountered when receiving data. In FIFO mode, the character with the error is
at the top of the FIFO.
6 OE Overrun error
0 Cleared when ULSR is read
1 Before URBR was read, it was overwritten with a new character. The old character is lost. In FIFO mode,
the receiver FIFO is full (regardless of the receiver FIFO trigger level setting) and a new character has
been received into the internal receiver shift register. The old character was overwritten by the new
character. Data in the receiver FIFO was not overwritten.
7 DR Data ready
0 Cleared when URBR is read or when all of the data in the receiver FIFO is read.
1 A character was received in the URBR or the receiver FIFO.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 18-17. ULSR Field Descriptions
Description
DUART
18-15