Freescale Semiconductor MPC8313E Family Reference Manual page 1109

Address
0x0_3110 I2C2DR—I
0x0_3114 I2C2DFSRR—I
0x0_311C– Reserved, should be cleared
0x0_31FF
2
17.3.1 I C Register Descriptions
This section describes the I
value they return when read. That is, the register should be programmed by reading the value, modifying
appropriate fields, and writing back the value. The return value of the reserved fields should not be
assumed, even though the reserved fields return zero. This does not apply to the I
(I2CnDR).
2
17.3.1.1 I C n Address Register (I2C n ADR)
Figure 17-2 shows the I2CnADR register, which contains the address to which the I
when addressed as a slave. Note that this is not the address that is sent on the bus during the address-calling
2
cycle when the I C module is in master mode.
Offset 0x0_3000
0
R
W
Reset
Table 17-4 describes the bit settings of I2CnADR.
Bits Name
0–6 ADDR Slave address. Contains the specific slave address that is used by the I
mode of the I
conditions that can cause I2C n SR[MIF] to be set, signaling an interrupt pending condition.
7 — Reserved, should be cleared
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
2
Table 17-3. I C Memory Map (continued)
2
I C Register
2
C2 data register
2
C2 digital filter sampling rate register
2
C registers in detail. Note that reserved bits should always be written with the
2
Figure 17-2. I C n Address Register (I2C n ADR)
Table 17-4. I2C n ADR Field Descriptions
2
C interface is slave mode for an address match. Note that an address match is one of the
Access
ADDR
All zeros
Description
Reset Section/Page
R/W 0x00 17.3.1.5/17-9
R/W 0x10 17.3.1.6/17-9
— —
2
Cn data register
2
C interface responds
Access: Read/write
6 7
—
2
C interface. Note that the default
2
I C Interfaces
—
17-5