Freescale Semiconductor MPC8313E Family Reference Manual page 1146

DUART
DMS FEN DMA Mode
0 0 0
0 1 0
1 0 0
1 1 1
DMS FEN DMA Mode
0 0 0
0 1 0
1 0 0
1 1 1
18.4 Functional Description
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the system clock signal.
The transmitter accepts parallel data with a write access to UTHR. In FIFO mode, the data is placed
directly into an internal transmitter shift register, or into the transmitter FIFO—see
Mode." The transmitting registers convert the data to a serial bit stream by inserting the appropriate
START, STOP, and optional parity bits. Finally, the registers output a composite serial data stream on the
channel transmitter serial data output (SOUT). The transmitter status may be polled or interrupt driven.
The receiver accepts serial data on the channel receiver serial data input (SIN), converts the data into
parallel format, and checks for START, STOP, and parity bits. In FIFO mode, the receiver removes the
START, STOP, and parity bits and then transfers the assembled character from the receiver buffer, or
receiver FIFO. This transfer occurs in response to a read of the UART receiver buffer register (URBR).
The receiver status may be polled or interrupt-driven.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
18-18
Table 18-23. UDSR[RXRDY] Set Conditions
RXRDY is set when there are no characters in the receiver FIFO or URBR.
RXRDY is set when the trigger level has not been reached and there has been no time out.
Table 18-24. UDSR[RXRDY] Cleared
RXRDY is cleared when there is at least one character in the receiver FIFO or URBR.
RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains
cleared until the receiver FIFO is empty.
Meaning
Meaning
Section 18.4.5, "FIFO
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