Freescale Semiconductor MPC8313E Family Reference Manual page 1197

Interface Mode
RTBI 1Gbps
SGMII 1 Gbps
SGMII 100 Mbps
SGMII 10 Mbps
TMII 200 Mbps
1
FIFM bit is not supported.
2
GMIIM bit is not supported.
15.5.3.1.8, 15-35
15.5.3.1, 15-35
15.5.3.1.9 TBI Physical Address Register (TBIPA)
The TBIPA, shown in
RTBI) for MII management configuration. The TBI registers are accessed at the offset of TBIPA. For
detailed descriptions of the TBI registers (the MII register set for the ten-bit interface) refer to
Section 15.5.4, "Ten-Bit Interface (TBI)."
Offset eTSEC1:0xB_0030; eTSEC2:0xB_1030
0
R
W
Reset
Table 15-15 describes the fields of the TBIPA register.
Bits Name
0–26 — Reserved
27–31 TBIPA This field is used to program the PHY address of the ten-bit interface's MII management bus. To access the
TBI register the user must write the TBIPA value to the MIIMADD [PHY Address] register located in the MAC
register section. PHY Address 0 is reserved. Refer to
(MIIMADD)."
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 13-30. eTSEC Interface Configurations (continued)
1 2
FIFM GMIIM TBIM
0 0 1
0 0 1
0 0 1
0 0 1
0 0 0
In Table 15-14, "DMACTRL Field Descriptions," change DMACTRL[TOD]
field definition by replacing the "1" definition with the following:
"1 eTSEC immediately fetches a new TxBD from ring 0."
Add section for register TBIPA, after Section 15.5.3.1.8, "DMA Control Register
(DMACTRL)."
Figure 15-10, is writable by the user to assign a physical address to the TBI (or
Figure 15-10. TBIPA Register Definition
Table 15-15. TBIPA Field Descriptions
ECNTRL Field
RPM R100M
1 0
0 0
0 1
0 0
0 0
—
All zeros
Description
Section 15.5.3.5.8, "MII Management Address Register
Revision History
MACCFG2 Field
RMM SGMIIM
0 0
0 1
0 1
0 1
0 0
Access: Read/Write
26 27
I/F Mode
10
10
01
01
01
31
TBIPA
A-19