Freescale Semiconductor MPC8313E Family Reference Manual page 1017

Micro-Frame
7
Numbers
HS Bus
FS/LS Bus
Figure 16-45. Frame Boundary Relationship Between HS Bus and FS/LS Bus
The simple projection, as
scheduling on both the beginning and end of a frame. In order to reduce the complexity for hardware and
software, the host controller is required to implement a one microframe phase shift for its view of frame
boundaries. The phase shift eliminates the beginning of frame and frame-wrap scheduling boundary
conditions.
The implementation of this phase shift requires that the host controller use one register value for accessing
the periodic frame list and another value for the frame number value included in the SOF token. These two
values are separate, but tightly coupled. The periodic frame list is accessed via the Frame List Index
Register (FRINDEX). Bits FRINDEX[2–0], represent the microframe number. The SOF value is coupled
to the value of FRINDEX[13–3]. Both FRINDEX[13–3] and the SOF value are incremented based on
FRINDEX[2–0]. It is required that the SOF value be delayed from the FRINDEX value by one
microframe. The one microframe delay yields a host controller periodic schedule and bus frame boundary
relationship as illustrated in
periodic start and complete-split transactions for full-and low-speed periodic endpoints, using the natural
alignment of the periodic schedule interface.
Figure 16-46 illustrates how periodic schedule data structures relate to schedule frame boundaries and bus
frame boundaries. To aid the presentation, two terms are defined. The host controller's view of the
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Frame
Boundary
0 1 2
SS CS
Figure 16-45 illustrates, introduces frame-boundary wrap conditions for
Figure 16-46. This adjustment allows software to trivially schedule the
3 4 5
CS CS SS CS
Universal Serial Bus Interface
6 7 0
CS CS CS
1
CS
16-75