Freescale Semiconductor MPC8313E Family Reference Manual page 1159

19.3.1 Overview
Table 19-1 lists signal properties.
Name
SPIMISO Master input slave output
SPIMOSI Master output slave input
SPICLK Input/output serial clock connected to the other SPICLK
SPISEL SPI slave select
19.3.2 Detailed Signal Descriptions
Table 19-2 describes the signals in detail.
Signal I/O
SPIMISO I/O Master input slave output
State
Meaning
Timing
SPIMOSI I/O Master output slave input
State
Meaning
Timing
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 19-1. Signal Properties
Function
Table 19-2. Detailed Signal Descriptions
Asserted—The data that has been transmitted/received from/to the SPI (depends if master or
slave mode) is high
Negated—The data that has ben transmitted/received from/to the SPI (depends if master or
slave mode) is low
Assertion—According to the SPICLK assertion/negation/in the middle of phase (depends on
SPMODE)
Negation—According to the SPICLK assertion/negation/in the middle of phase (depends on
SPMODE)
Asserted—The data that has been transmitted/received from/to the SPI (depends if master or
slave mode) is high
Negated—The data that has ben transmitted/received from/to the SPI (depends if master or
slave mode) is low
Assertion—According to the SPICLK assertion/negation/in the middle of phase (depends on
SPMODE)
Negation—According to the SPICLK assertion/negation/in the middle of phase (depends on
SPMODE)
Reset
—
—
—
—
Description
Serial Peripheral Interface
Pull Up
Required in open drain mode
Required in open drain mode
Required in open drain mode
Required in open drain mode
19-7