Freescale Semiconductor MPC8313E Family Reference Manual page 1226

Powerquicc ii pro integrated processor

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Option Register Attributes

Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV

10.4.2.3.2, 10-51

10.4.3.4.1, 10,70

10.4.3.4.2, 10-71

10.4.4.1.2, 10-74

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

In the second paragraph, third sentence, changed to read: 'ORn[CSNT], along

with ORn[TRLX], control ...'.

In Table 10-36, changed the setting for field SCY to read: From por_cfg_scy[1:3].

Changed step 4, first paragraph, to read:

4. If ECC checking is enabled, the FCM recovers from the spare region the stored

ECC for each 512-byte block of boot data. The boot block must be prepared

with ECC protection. During ECC generation, software should use

FMR[ECCM] = 0 for small-page devices, and FMR[ECCM] = 1 for large-page

Second paragraph, replaced with the following:

By default, all local bus refreshes are performed using the refresh pattern of

UPMA. This means that if refresh is required, MAMR[RFEN] must be set. It also

means that only one refresh routine should be programmed and be placed in

UPMA, which serves as the refresh executor. Any banks assigned to a UPM are

provided with the common UPMA refresh pattern if the RFEN bit of the

corresponding UPM is set, concurrently. UPMA assigned banks, therefore, always

receive refresh services when MAMR[RFEN] is set, while UPMB and UPMC

Signal Timing (LCLK Clock Cycles)

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