Freescale Semiconductor MPC8313E Family Reference Manual page 1107

Additionally, the following three I
• START condition. This condition denotes the beginning of a new data transfer (each data transfer
contains several bytes of data) and awakens all slaves.
• Repeated START condition. A START condition that is generated without a STOP condition to
terminate the previous transfer.
• STOP condition. The master can terminate the transfer by generating a STOP condition to free the
bus.
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17.2 I C External Signal Descriptions
The following sections give an overview of signals and provide detailed signal descriptions.
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17.2.1 I C Signal Overview
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The I C interface uses the SDAn and SCLn signals, described in
the signal patterns driven on SDAn represent address, data, or read/write information at different stages of
the protocol.
Signal Name Idle State I/O
Serial Clock High
(SCL1,
SCL2)
Serial Data High
(SDA1,
SDA2)
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17.2.2 I C Detailed Signal Descriptions
SDAn and SCLn, described in
devices connected to these signals must have open-drain or open-collector outputs. The logic AND
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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C–specific states are defined for the I
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Table 17-1. I C Interface Signal Descriptions
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I When the I C module is idle or acts as a slave, SCL n defaults as an input. The unit uses SCL n
to synchronize incoming data on SDA n . The bus is assumed to be busy when SCL n is detected
low.
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O As a master, the I C module drives SCL n along with SDA n when transmitting. As a slave, the
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I C module drives SCL n negates for data pacing.
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I When the I C module is idle or in a receiving mode, SDA n defaults as an input. The unit
receives data from other
detected low.
O When writing as a master or slave, the I
Table 17-2, serve as a communication interconnect with other devices. All
Table
State Meaning
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I C
devices on SDA n . The bus is assumed to be busy when SDA n is
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C module drives data on SDA n synchronous to SCL n .
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C interface:
17-1, for data transfer. Note that
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I C Interfaces
17-3