Freescale Semiconductor MPC8313E Family Reference Manual page 1242

Revision History
16.3.2.13, 16-25
23 PHCD PHY low power suspend. This bit is not defined in the EHCI specification.
Host mode:
• The PHY can be put into low power suspend —when the downstream device has been put into suspend
mode or when no downstream device is connected. Low power suspend is completely under the control of
software.
Device mode:
• The PHY can be put into low power suspend—when the device is not running (USBCMD[RS] = 0b) or
suspend signaling is detected on the USB. Low power suspend will be cleared automatically when the
resume signaling has been detected or when forcing port resume.
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Note: If there is no clock connected to the USBDR_CLK signals, PHCD must be set and the following
registers should not be written: DEVICE_ADDR/PERIODICLISTBASE, PORTSC, ENDPTCTRL0,
ENDPTCTRL1, ENDPTCTRL2.
16.3.2.15, 16-31
16.3.2.24, 16-38
16.3.2.26, 16-40
31 rd_prefetch_val Selects whether 32 bytes or 64 bytes are fetched during burst read transactions at the system
16.3.2.27, 16-41
29 USB_EN
16.5.6, 16-59
16.6.1, 16-65
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-64
In Table 16-22, changed the description for bit 23 with the following:
In Table 16-24, "OTGSC Register Field Descriptions," corrected bit field
description of field 7–5 from "Reserved, should be cleared" to "Reserved, writes
should preserve reset value."
In fourth paragraph, second sentence, changed as follows:
If AGE_CNT_THRESH is equal to zero, priority state one is always chosen.
In Table 16-35, bit 31, changed the description to read as follows:
interface. When this input is LOW 64 bytes are fetched and when it is HIGH 32 bytes are fetched.
The setting of rd_prefetch_val must match the setting of the larger of TXPBURST and RXPBURST
fields in the BURSTSIZE register. If either of these fields is 64 bytes, then rd_prefetch_val must be
left cleared. Otherwise, this value should be set.
0 64-byte fetch
1 32-byte fetch
In Table 16-36, bit 29, changed the description to read as follows:
UTMI mode: This bit is used to enable the USB interface. It must be set before setting RS bit in
USB CMD register.
1 Enable
0 Disable
ULPI mode: In safe mode, all USB interface signals are put into input mode or driven inactive,
except for SUSPEND_STP which is driven high. Also, the input signal DIR is forced to appear high
to the controller. This prevents any start-up problems that otherwise could occur if the PHY and
the controller take significantly different times to complete power-on reset.
1 Normal operation
0 Safe mode
In Figure 16-40, for RL, changed to bits 31–28, C to bit 27, and Maximum Packet
Length to bits 26–16.
In first paragraph, first sentence, removed 'as illustrated in Table 25'. Replaced
the second with the following:
After a hardware reset, only the operational registers will be at their default values.
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