Freescale Semiconductor MPC8313E Family Reference Manual page 1218

Revision History
3.1, 3-2
3.1, 3-7
TSEC_MDC Ethernet
management
data clock
1
The LB_POR_CFG_BOOT_ECC_DIS function will be selected on the TSEC_MDC pin whenever HRESET is asserted; the
pin will act as TSEC_MDC at all other times. The reset block will sample this signal on PORESET negation only; the sampled
value is then passed to the eLBC controller to enable/disable ECC checking during boot time.
3.1, 3-7
TSEC_TMR_CLK 1588 external timer
reference clock
input
TSEC_TMR_GCLK 1588 timers
TSEC_TMR_PP1 1588 timer pulse per
period 1
TSEC_TMR_PP2 1588 timer pulse per
period 2
TSEC_TMR_PP3 1588 timer pulse per
period 3
TSEC_TMR_TRIG1 1588 external timer
trigger input 1
TSEC_TMR_TRIG2 1588 external timer
trigger input 2
TSEC_TMR_ALARM1 1588 timer; current
time is equal to or
greater than alarm
time comparator
register
TSEC_TMR_ALARM2 1588 timer; current
time is equal to or
greater than alarm
time comparator
register
3.1, 3-9
LB_POR_CFG_BOOT Boot time ECC
_ECC_DIS checking
Chapter 4
4.1.1, 4-1
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-40
In Figure 3-1, added LB_POR_CFG_BOOT_ECC_DIS to the TSEC_MDC
signal.
In Table 3-1, changed TSEC_MDC row and added a footnote as follows:
Ethernet
management
In Table 3-1, added the following rows after TSEC_MDIO:
eTSEC
eTSEC
eTSEC
eTSEC
eTSEC
eTSEC
eTSEC
eTSEC
eTSEC
In Table 3-1, added the following row after LCLK[0:1]:
eLBC
Throughout chapter—Editing done for consistency.
In Table 4-1, in the Description column for SRESET, changed the Timing,
Negation statement to read: 'Occurs after being serviced.'
1 O 15-2/15-8
1 I 15-2/15-8
1 O 15-2/15-8
1 O 15-2/15-8
1 O 15-2/15-8
1 O 15-2/15-8
1 I 15-2/15-8
1 I 15-2/15-8
1 O 15-2/15-8
1 O 15-2/15-8
1 1 —
LB_POR_CFG_BOOT
1
_ECC_DIS
UART_SOUT2/LA10
UART_SIN2/LA11
UART_CTS[2]/LA12
UART_RTS[2]/LA13
GPIO14/LA9
IIC1_SDA/LA14
LA7
LA8
IIC1_SCL/LA15
TSEC_MDC
Freescale Semiconductor
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