Freescale Semiconductor MPC8313E Family Reference Manual page 1232

Revision History
15.5.3.1.6, 15-32
28 R100M RGMII/RMII 100 mode. This bit is ignored unless SGMIIM, RPM or RMM are set and MACCFG2[I/F
Mode] is assigned to 10/100 (01).
0 RGMII is in 10 Mbps mode;
SGMII is in 10 Mbps mode, and every 100th SGMII Reference clock is used to transfer data
1 RGMII is in 100 Mbps mode;
SGMII is in 100 Mbps mode, and every 10th SGMII Reference clock is used to transfer data
This bit must be cleared for 1-Gbps SGMII operation.
15.5.3.3.1, 15-49
15.5.3.3.7, 15-57
0 GPI General purpose interrupt. When a property matches the value in the RQPROP entry at this index, and
REJ = 0 and AND = 0, the filer will instruct the Rx descriptor controller to set IEVENT[FGPI] when the
corresponding receive frame is written to memory.
If the timer is enabled (TMR_CTRL[TE] = 1), then TMR_PEVENT[RXP] will also be set.
15.5.3.3.8, 15-58
A value in the length/type field greater than 1500 and less than 1536 is treated as a type encoding by the parser. Since no
4. The MPLS tagged packets—In this case, one can use arbitrary extraction bytes to compare to the actual ethertype if a filer
Note:
15.5.3.5.1, 15-67
15.5.3.5.2, 15-67
Pad and append CRC. This bit is cleared by default. This bit must be set when in half-duplex mode (MACCFG2[Full Duplex]
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-54
In Table 15-10, changed the description in bit 28 to the following:
RMII is in 10 Mbps mode, and every 10th RMII Reference clock is used to transfer data
RMII is in 100 Mbps mode, and data is transferred on every Reference clock
In Table 15-27, bit 29, in the Description column, added the following sentence:
Note that frames less than or equal to 16B in length are always silently dropped.
In Figure 15-29, changed bit 0 to GPI and the reset value to 'undefined'.
In Table 15-33, add the following for bit 0, GPI:
In Figure 5-29, changed the reset value to 'undefined'.
In Table 15-34, bits 16-31, in the Description column, replaced the fourth
paragraph with the following:
recognized types exist in this range, the controller will not parse beyond the length/type field of any
such frame.
Replaced item 4 and added the following text:
rule is intending to file based on an MPLS label existence.
Users of the eTSEC parser/filer should be aware of a difference in behavior between rev 1 and rev
2 silicon in cases where the Ethernet type/length field contains a value between 1500 and
1536.
In rev 2 silicon, values between 1500 and 1536 are interpreted as a type. Since there are
currently no valid types in this range publicly defined by IANA, the controller will not parse
beyond the length/type field of any such frame.
If the same packet is encountered with rev 1 silicon, parser/filer behavior is different. With
rev 1 silicon, such packets are treated as payload length. S/W must confirm the parser and
filer results by checking the type/length field after the packet has been written to memory to
see if it falls in this range.
In Table 15-39, bits 26 and 27, add the following statement in the Description
column after the first paragraph: Must be 0 if MACCFG2[Full Duplex] = 0.
In Table 15-40, bits 16–19, in the Description column, added the following
sentence: 'Values from 0x3 to 0xF are supported by the controller.'
For bit 29, in the Description column, changed the first paragraph to read:
is cleared).
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