Freescale Semiconductor MPC8313E Family Reference Manual page 1210

Revision History
16.5.7.2, 16-67
16.6.1, 16-68
16.6.2, 16-69
16.6.4.1, 16-71
Port Status and Signaling Type
Port disabled, resume K-State received
Port suspended, Resume K-State
received
Port is enabled, disabled or suspended,
and the port's PORTSC[WKDS], is set. A
disconnect is detected.
Port is enabled, disabled or suspended,
and the port's PORTSC[WKDS], is
cleared. A disconnect is detected.
Port is not connected and the port's
PORTSC[WKCN] bit is a one. A connect
is detected.
Port is not connected and the port's
PORTSC[WKCN] bit is a zero. A connect
is detected.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-32
In Table 16-63, "FSTN Back Path Link Pointer," modify the field description of
bit 0 to say as follows:
"Terminate.
0 Link pointer is valid (that is, the host controller may use bits 31–5 as a valid
memory address). This value also indicates that this FSTN is a Save-Place
indicator.
1 Link pointer field is not valid (that is, the host controller must not use
bits 31–5 as a valid memory address). This value also indicates that this FSTN
is a Restore indicator."
Remove the following sentence in the second paragraph:
"After a hardware reset, only the operational registers will be at their default
values."
Add the following sentence to the end of first paragraph:
"The Configured Flag and Port Power Control bits are always 1'b1 in Host Mode.
The PPE always follows the state of Port Power (PP) bit that is, if PP is 0, PPE
will be 0 and if PP is 1, PPE will be 1."
In Table 16-64, "Behavior During Wake-Up Events," modify the following bit
names in "Port Status and Signaling Type" column:
WKDSCNNT_E to PORTSC[WKDS]
WKCNNT_E to PORTSC[WKCN]
WKOC_E to PORTSC[WKOC]
The Table now reads:
Table 16-64. Behavior During Wake-Up Events
No effect
Resume reflected downstream on signaled port.
PORTSC[FPR] is set. USBSTS[PCI] is set.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
Signaled Port Response
Device State
D0 not D0
N/A N/A
[1], [2] [2]
[1], [2] [2]
[1], [3] [3]
[1], [2] [2]
[1], [3] [3]
Freescale Semiconductor