Freescale Semiconductor MPC8313E Family Reference Manual page 1014

Universal Serial Bus Interface
controller evaluates the Suspend bit. The host controller must evaluate the Suspend bit at least every frame
boundary.
System software can initiate a resume on the suspended port by writing a one to PORTSC[FPR]. Software
should not attempt to resume a port unless the port reports that it is in the suspended state. If system
software sets PORTSC[FPR] when the port is not in the suspended state, the resulting behavior is
undefined. In order to assure proper USB device operation, software must wait for at least 10 milliseconds
after a port indicates that it is suspended (Suspend bit is a one) before initiating a port resume through
PORTSC[FPR]. When PORTSC[FPR] is set, the host controller sends resume signaling down the port.
System software times the duration of the resume (nominally 20 milliseconds) then clears PORTSC[FPR].
When the host controller receives the write to transition PORTSC[FPR] to zero, it completes the resume
sequence as defined in the USB specification, and clears both PORTSC[FPR] and PORTSC[SUSP].
Software-initiated port resumes do not affect the port change detect bit (USBSTS[PCI]) nor do they cause
an interrupt if USBINTR[PCE] (port change interrupt enable) is a one. When a wake event occurs on a
suspended port, the resume signaling is detected by the port and the resume is reflected downstream within
100 µsec. The port's PORTSC[FPR] bit is set and USBSTS[PCI] is set. If USBINTR[PCE] is a one, the
host controller issues a hardware interrupt.
System software observes the resume event on the port, delays a port resume time (nominally 20
milliseconds), then terminates the resume sequence by clearing PORTSC[FPR] in the port. The host
controller receives the write of zero to PORTSC[FPR], terminates the resume sequence and clears
PORTSC[FPR] and PORTSC[SUSP]. Software can determine that the port is enabled (not suspended) by
sampling the PORTSC register and observing that the SUSP and FPR bits are zero. Software must ensure
that the host controller is running (that is, USBSTS[HCH] is a zero), before terminating a resume by
clearing the port's PORTSC[FPR] bit. If HCH is a one when PORTSC[FPR] is cleared, then SOFs will not
occur down the enabled port and the device will return to suspend mode in a maximum of 10 milliseconds.
Table 16-64 summarizes the wake-up events. Whenever a resume event is detected, USBSTS[PCI] is set.
If USBINTR[PCE] (port change interrupt enable) is a one, the host controller also generates an interrupt
on the resume event. Software acknowledges the resume event interrupt by clearing the USBSTS[PCI].
Port Status and Signaling Type
Port disabled, resume K-State received
Port suspended, Resume K-State
received
Port is enabled, disabled or suspended,
and the port's PORTSC[WKDS], is set. A
disconnect is detected.
Port is enabled, disabled or suspended,
and the port's PORTSC[WKDS], is
cleared. A disconnect is detected.
Port is not connected and the port's
PORTSC[WKCN] bit is a one. A connect
is detected.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-72
Table 16-64. Behavior During Wake-Up Events
Signaled Port Response
No effect
Resume reflected downstream on signaled port.
PORTSC[FPR] is set. USBSTS[PCI] is set.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
Device State
D0 not D0
N/A N/A
[1], [2] [2]
[1], [2] [2]
[1], [3] [3]
[1], [2] [2]
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