Freescale Semiconductor MPC8313E Family Reference Manual page 1158

Powerquicc ii pro integrated processor

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Serial Peripheral Interface

All signals are open-drain.

For a multiple-master configuration with more than two masters, SPISEL and SPIE[MME]

do not detect all possible conflicts.

It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example).

SELOUT x signals are implemented in software with general-purpose I/O signals.

The SPI can transfer a single character at much higher rates—input clock/4 in master mode and input

clock/2 in slave mode, and subjected to the timing parameters of the interconnected devices, and board

trace delays. Gaps should be inserted between multiple characters to keep from exceeding the maximum

sustained data rate.

External Signal Descriptions

The SPI's four wire interface consists of transmit, receive, clock, and slave select.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Figure 19-3. Multiple-Master Configuration

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